A800(DOCS)		Optical Printer Control System		A800(DOCS)


NAME
    A800 - Seriss Corp. A800 stepper motor control card 

DESCRIPTION
    The A800 card is a "short slot" ISA card for the IBM PC that can
    generate steps/direction pulse streams to control up to 8 stepper
    motors at once.
    
    The card uses two PIC chips to manage the stepper pulse generation.
    The PIC's firmware and MS-DOS driver "A800DRV.COM" source code are
    open source and available from:

        https://github.com/erco77/a800-opcs-pic-asm

    OPCS communicates with the A800 card by way of the MS-DOS device driver
    "A800DRV.COM", which provides a standard low level interface to the
    card that OPCS can make use of to run the motors efficiently.

    The A800DRV.COM driver must be loaded *before* running the OPCS
    software. This can be installed either by the AUTOEXEC.BAT,
    or by a separate batch script that invokes OPCS. 

    If the A800 card's jumpers are default (BaseAddr=300 and IRQ=5),
    then you can install the driver with just:

        a800drv

CONFIGURING THE BASEADDR AND IRQ
    In OPCS K1.xx, the a800 card did not exist and is not supported.

    In OPCS K2.00 through K2.09, the base address is configured in
    OPCSDEFS.OPC with the 'baseaddr' command. IRQ not configurable.

    In OPCS K2.10 and up, the A800DRV.COM driver allows both the
    base address and IRQ to be configured on the command line.
    The default would be:

        a800drv -b300 -i5           <-- Sets base address=0300h, IRQ=5
                   |    |
                   |    IRQ=5
                   Base Addr=300

    ..and if your A800 jumpers are set differently, then specify
    matching values accordingly. e.g. if the card's jumpers are
    set to BaseAddr=340 and IRQ=6, then start the driver with:

        a800drv -b340 -i6

    To list the A800DRV driver's options, run 'a800drv -help'.
    If it does not show a list of options, then it is an older version
    that does not support command line options.

TECHNICAL SYNOPSIS
    When the software wants to move a motor, it provides 8 separate
    12 bit velocity values, one per motor channel. And 107 of these
    velocity values are sent per second to the card using the hardware
    interrupt on IRQ 5.

    Currently only 8 bits of the 12bit value are used for motor speeds.
    i.e. the lowest velocity is 1 (107 Hz) and the highest velocity is
    255 (27,285 Hz). Values above 255 are clipped by the hardware,
    as the PIC chips are limited by their speed. The high bit (0x8000)
    is the motor direction bit; 0=foward, 1=reverse. 

    The software has to keep up with this transimission rate, otherwise
    it will loose track of the motor positions. The A800DRV.COM device
    driver provides a 64k ring buffer for the motor velocities that OPCS
    updates in realtime while the motors are running.

    The OPCS software and A800DRV.COM use INT 99h to intercommunicate,
    providing the address of the ring buffer, and start/stop commands.

    The A800 card generates 107 interrupts per second to the A800DRV.COM
    driver, each interrupt feeds 8 velocities from the tail of the ring
    buffer to the A800 card, and increments the tail's index to point
    to the next 8 values in the ring buffer. Meanwhile, the OPCS software
    feeds velocities into the head of the ring buffer, always keeping ahead
    of the tail. If the tail catches up to the head prematurely, this
    causes a SYNC FAULT error, which should never happen unless something
    is wrong with the computer.
♀
OPCS A800 CARD
==============
This card controls 8 axes and is a half sized IBM PC ISA card.
For complete info on this card, see: http://seriss.com/opcs/a800

        *** A800 ***
	      _________________________________________________
	     | _____    __________   __________        A800    |
	     ||16Mhz|  |  CPU2    | |  CPU1    |       REV-A1  | 
	     ||Xtal |  |__________| |__________|           ____|_
	     ||_____|                     ____   74HCT04  |    | |
	     |                           |    |  ______   |    | |
	     |                           |8255| |______|  |    | |
	     |                           |    |  ______   |    | | DB-37
	     |              BASE         |    | |______|  |    | | Connector
	     |   ______     ADDR         |    |  ______   |    | |
	     |  |______|     ::  IRQ     |    | |______|  |    | |
	     |  _______      ::  ::      |    |           |    | |
	     | |_______|     ::  ::      |____|           |____|_|
	     |               ::  ::                            |
	     |_________________________                     ___|
	                               |...................|
	                                ||||||||||||||||||||

     DB-37 Connector (similar to Kuper):

         PIN#   SIGNAL   PIN SIGNAL
        --------------------------------
           1  - N/C      20 - +5VDC
           2  - STEP A   21 - DIR A
           3  - STEP B   22 - DIR B
           4  - STEP C   23 - DIR C
           5  - STEP D   24 - DIR D
           6  - STEP E   25 - DIR E
           7  - STEP F   26 - DIR F  (*) = JP3 configures DB37 Pin#19:
           8  - STEP G   27 - DIR G        "+5"   - Makes Pin #19 +5 VDC
           9  - STEP H   28 - DIR H        "GND"  - Makes Pin #19 GND (default)
           10 - N/C      29 - N/C  
           11 - N/C      30 - N/C  
           12 - N/C      31 - N/C    NOTE: When fitted with 74LS07 chips,
           13 - N/C      32 - N/C          outputs are OPEN COLLECTOR TTL.
           14 - N/C      33 - N/C   
           15 - N/C      34 - N/C          When those chips are replaced with
           16 - N/C      35 - N/C          74ALS1034N, outputs swing a full
           17 - N/C      36 - N/C          +5/GND and are CMOS/TTL compatible.
           18 - N/C      37 - N/C  
           19 - GND(*)             

BASE ADDRESS (JP1)
==================
    Closeup of the 'BASE ADDRESS' jumpers (JP1), which sets the base
    address of the 8255 chip's I/O port registers:

		  ___________
		 | BASE ADDR |
		 |___________|
		 |           |
		 |  200  o o |
		 |  240  o o |
		 |  280  o o |
		 |  2C0  o o |
		 |  300  o o <-- Default jumper for 300 across these two pins
		 |  340  o o |
		 |  380  o o |
		 |  3C0  o o |
		 |___________|
		      JP1

	    A800 Base Address Jumpers

        Always defer to the board's labeling (if any), as the board
        designs may have changed since this document's writing (May 2020).

    DEFAULTS:
    This board has labels for the BASE ADDRESS and IRQs:
        "300"  is the default base address (5th pair of pins from top jumpered).
        "IRQ5" is the default IRQ (4th pair of pins from top jumpered).

DB-37 OUTPUT SIGNALS
====================
    The STEPS output are normally high (+5) during idle,
    and fall low (GND) to pulse the motor a single step. 

    The outputs for DIR (direction) are logic hi (+5) for forward,
    and logic low (GND) for reverse.

    The output signals can either be CMOS hi/low levels, or can be
    "open collector" (where logic 'hi' is 'open', and logic low is gnd).
    Which it is depends on the chips installed in the three chip positions
    to the left of the DB-37 connector on the A800 board:

	74HCT04 -- CMOS high/low levels (default)
    	74LS07  -- Open Collector

    For controlling the modern DM542 and FMD27400 motor drivers,
    the 74HCT04 chips are recommended in these positions.

    For Centent and Gecko drives, traditionally 74LS07 chips were used,
    but will probably also work with the 74HCT04's.

    While both chips work on all drives, analysis with an oscilloscope
    monitoring the stepper drive inputs may reveal one chip is better
    than the other for noise reduction. With 6' cables, 74HCT04 seems
    the best choice.

    Always defer to the board's silk screen labelling, as the board
    designs may change since this document's writing (May 2020).


HISTORY
    Greg Ercolano designed this card in May/June 2020, and the driver
    software, A800DRV.COM. This card uses "PIC chips", which are 
    programmed with firmware written in the processor's native assembly
    language for speed and consistent timing for generating the steps
    and direction motor signals.

SEE ALSO
    RTMC16(DOCS) - notes on the Kuper Controls RTMC16 motor control card
    RTMC48(DOCS) - notes on the Kuper Controls RTMC48 motor control card
    8255(DOCS)   - how to control 8255 based digital I/O cards
    KUPER(DOCS)  - documentation on the kuper card connectors


ORIGIN
    Gregory Ercolano, Alhambra, California 06/01/20
© Copyright 1997 Greg Ercolano. All rights reserved.